1. Field of the Invention
The present invention relates to direct block access storage devices such as hard disk drives (HDDs) and solid state disks (SSDs), and, in particular, to decoupling of host data transfer boundaries (e.g., host frame size) from data storage boundaries (e.g., chunk size).
2. Description of the Related Art
Flash memory is a type of non-volatile memory that is electrically erasable and re-programmable. Flash memory is primarily used in memory cards and USB flash drives for general storage and transfer of data between computers and other digital products. Flash memory is a specific type of electrically erasable programmable read-only memory (EEPROM) that is programmed and erased in large blocks. One commonly employed type of flash memory technology is NAND flash memory. NAND flash memory forms the core of the flash memory available today, especially for removable universal serial bus (USB) storage devices known as USB flash drives, as well as most memory cards. NAND flash memory exhibits fast erase and write times, requires small chip area per cell, and has high endurance. However, the I/O interface of NAND flash memory does not provide full address and data bus capability and, thus, generally does not allow random access to memory locations.
There are three basic operations for NAND devices: read, write and erase. The read and write operations are performed on a page by page basis. Page sizes are generally 2N bytes, where N is an integer, with typical page sizes of, for example, 2,048 bytes (2 kb), 4,096 bytes (4 kb), 8,192 bytes (8 kb) or more per page. Pages are typically arranged in blocks, and an erase operation is performed on a block by block basis. Typical block sizes are, for example, 64 or 128 pages per block. Pages must be written sequentially, usually from a low address to a high address. Lower addresses cannot be rewritten until the block is erased.
A hard disk is addressed linearly by logical block address (LBA). A hard disk write operation provides new data to be written to a given LBA. Old data is over-written by new data at the same physical LBA. NAND flash memories are accessed analogously to block devices, such as hard disks. NAND devices address memory linearly by page number. However, each page might generally be written only once since a NAND device requires that a block of data be erased before new data is written to the block. Thus, for a NAND device to write new data to a given LBA, the new data is written to an erased page that is a different physical page than the page previously used for that LBA. Therefore, NAND devices require device driver software, or a separate controller chip with firmware, to maintain a record of mappings of each LBA to the current page number where its data is stored. This record mapping is typically managed by a flash translation layer (FTL) in software that might generate a logical-to-physical translation table. The flash translation layer corresponds to the media layer of software and/or firmware controlling an HDD.
Storage devices such as HDDs and SSDs commonly employ a separate media controller chip to facilitate use of the storage device. In general, such a media controller chip might process operations of the storage device, for example read or write operations. The media controller chip might be implemented as a system on chip (SoC) having one or more processors. One or more firmware modules will be installed to run on each of the one or more processors, with each firmware module including one or more sub-components. For example, the media controller firmware might include firmware modules and sub-components to process one or more diagnostic operations.
An HDD or SSD media controller might operate in compliance with one or more host communication protocols, for example, the Small Computer System Interface (“SCSI”) protocol, the Serial Attached SCSI (“SAS”) protocol, or the Serial Advanced Technology Attachment (“SATA”) protocol. The SCSI protocol is a communications protocol where multiple components are connected to the same bus and a process of arbitration determines which device gets access to the bus at any point in time. The SCSI command set is described in the SCSI Primary Commands standard (SCSI Primary Commands—SPC-3 Revision 23, May 4, 2005, hereinafter “SCSI SPC standard,” included by reference herein). The SAS protocol is a serial protocol that employs the standard SCSI command set, but is point-to-point, meaning that each SAS device is connected by a dedicated bus to a device that originates requests (an initiator). The SATA protocol is a serial protocol that uses the standard ATA command set. The ATA command set is described in the AT attachment standard (AT Attachment 8—ATA/ATAPI Command Set (ATA8-ACS) Revision 4a, May 21, 2007, hereinafter “ATA standard,” included by reference herein). Although, in some applications, it might be desirable to employ SAS and SATA devices interchangeably, in general, separate host interface modules within the media controller chip might be required.
Since an HDD or SSD might receive one or more commands such as read, write or erase operations, before a previously received command has completed, a queue might generally maintain a list of commands received while a previous command is being processed. In storage devices operating in accordance with the SCSI standard, a control field, such as the SCSI Queue Algorithm Modifier (QAM) field, might be employed to indicate whether reordering of the queue of received commands is permitted. As defined by the SCSI Primary Commands standard (SPC-3, Section 7.4.6, pg. 285, 2005, included by reference herein), when the QAM field has a value of zero, command reordering is restricted, and queued commands must be processed in the order in which they are received. When the QAM field has a value of one, command reordering is permitted, and the storage device may process queued commands in any order. Further, a control field, such as the SCSI Task Attribute field, might be employed to indicate how commands are queued. As defined by the SCSI Architecture Model (SAM-5, Section 8.9, pp. 123-127, 2009, included by reference herein), the Task Attribute field defines the attributes SIMPLE, ORDERED, HEAD OF QUEUE, or ACA, which indicate how a received command should be queued. For example, a received command having the HEAD OF QUEUE attribute is placed at the head of the queue, ahead of any previously queued commands.
Diagnostic operations are typically small functions implemented in the media controller firmware. Each diagnostic operation might perform a specific task to help debug a given device problem. Common diagnostic operations might, for example, include reading or writing a register, performing a test, and reporting device status. A request for the media controller to perform a diagnostic operation might be initiated from one or more different sources. For example, a typical SAS or SATA host device might request a diagnostic operation be performed. Further, other host types might be employed such as, for example, USB, and, in a design and development environment, other communication links might be employed. Typically, the media controller handles diagnostic operations from different sources independently. Thus, every firmware layer generally might include a module for each diagnostic operation, and often each firmware layer might include separate module implementations for each type of source.
A universal asynchronous receiver/transmitter (UART) is often used during design and development of an embedded device to provide a way to issue commands to the embedded device and transfer and display logging information indicating the status of the embedded device. A UART is often employed in conjunction with a computer serial port operating according to the RS-232 standard. For RS-232 UARTs to transfer binary data, the binary data is typically converted to ASCII (e.g., through Base64 encoding), or the UART switches into a binary mode to transfer the binary data. Both of these methods add complexity and inefficiency to the implementation. Further, typical control software or firmware of RS-232 UARTs do not allow for asynchronous transfer of “datagram” type messages interleaved with their main “command processing” messages.